An FPGA based implementation of G.729

The main objective of this article is to present the implementation and simulation of a conjugate structure algebraic code excited linear prediction speech coder (CS-ACELP) based upon ITU-T's G.729 recommendation and to optimize it for real-time implementation on an FPGA. The suggested architecture is characterized by pipelining and parallel operation of functional units, using fixed point two's complement representation for integers. The design was functionally verified by utilizing the ModelSim software package from Mentor Graphics Corporation Company and then synthesized by Xilinx Integrated Software Environment (ISE) 6.1 software. Preliminary results show that the overall system delay is less than 2 ms for each frame.